I want to share a synthesisable random number generator in VHDL in this post. I had previously created a LFSR(Linear feedback shift register) based random number generator. But it was faulty, as pointed out by an expert in the field, Chris, who had happen to see the code. The issue was that the tap values I had taken for feeding back the shift register was wrong. This resulted in a non-maximum length sequence. For example as Chris pointed out, in the older code, when the register size is 32 bits the sequence period is 2^21-1 and not 2^32-1 as I had claimed.
So I have written another code which uses the correct tap values to ensure that the sequence generated is of maximum length. The project is uploaded at opencores.org and can be downloaded for free. The code take cares of register sizes from 3 bit to 168 bits. The tap values were referred from a Xilinx documentation about LFSR.
The project can be downloaded from, Random number generator using LFSR. After downloading, extract the contents of the zip file. The codes and documentation is available in the folder named "trunk".
Currently the project is in alpha stage. Please let me know if you find any bugs in the code
So I have written another code which uses the correct tap values to ensure that the sequence generated is of maximum length. The project is uploaded at opencores.org and can be downloaded for free. The code take cares of register sizes from 3 bit to 168 bits. The tap values were referred from a Xilinx documentation about LFSR.
The project can be downloaded from, Random number generator using LFSR. After downloading, extract the contents of the zip file. The codes and documentation is available in the folder named "trunk".
Currently the project is in alpha stage. Please let me know if you find any bugs in the code
Hope this project is useful.
