Generating random numbers in a VHDL testbench

I have written two posts about random number generation in vhdl before. But these were written from a synthesisable point of view. So they are a bit complex. But if you are looking just for a simulatable code( for example to be used in a testbench) then there is a much simpler way to generate random numbers.

We use the procedure named UNIFORM which is defined in the IEEE library named math_real. Without too much explanation I will share the code with you.

library ieee;
use ieee.math_real.all;

entity rand_gen is
end rand_gen;

architecture behavior of rand_gen is 

signal rand_num : integer := 0;

begin

process
    variable seed1, seed2: positive;               -- seed values for random generator
    variable rand: real;   -- random real-number value in range 0 to 1.0  
    variable range_of_rand : real := 1000.0;    -- the range of random values created will be 0 to +1000.
begin
    uniform(seed1, seed2, rand);   -- generate random number
    rand_num <= integer(rand*range_of_rand);  -- rescale to 0..1000, convert integer part 
    wait for 10 ns;
end process;

end behavior;


The code generates random numbers with a time gap of 10 ns between two successive numbers. The variable named range_of_rand defines how big the random number can get. The uniform procedure generates numbers between 0.0 and 1.0. So to generate big numbers you just multiply it by a real number( in the above code 1000.0 ) and type cast it to an integer.

Using functions like conv_std_logic_vector or to_unsigned you can convert these random integers into binary format vectors. Remember to declare the required additional libraries in such cases.

Note :- The code was simulated using Xilinx ISE 13.1 Webpack. It should be able to work in other 

VHDL: LFSR Based Random Number Generator

     I want to share a synthesisable random number generator in VHDL in this post. I had previously created a LFSR(Linear feedback shift register) based random number generator. But it was faulty, as pointed out by an expert in the field, Chris, who had happen to see the code. The issue was that the tap values I had taken for feeding back the shift register was wrong. This resulted in a non-maximum length sequence. For example as Chris pointed out, in the older code, when the register size is 32 bits the sequence period is 2^21-1 and not 2^32-1 as I had claimed.

    So I have written another code which uses the correct tap values to ensure that the sequence generated is of maximum length. The project is uploaded at opencores.org and can be downloaded for free. The code take cares of register sizes from 3 bit to 168 bits. The tap values were referred from a Xilinx documentation about LFSR.

    The project can be downloaded from, Random number generator using LFSR. After downloading, extract the contents of the zip file. The codes and documentation is available in the folder named "trunk".
Currently the project is in alpha stage. Please let me know if you find any bugs in the code

Hope this project is useful.