VHDL: Asynchronous D Flip-Flop with Testbench

    As per the request from few readers I have decided to post some simple VHDL codes for people who are just starting out with VHDL. This, here is a D Flip-Flop with Asynchronous Clear and Clock Enable(posedge clock). The code is well commented I believe, so I wont bore you with more explanations.

Asynchronous D flipflop:

--library declaration for the module.
library ieee;
use ieee.std_logic_1164.all;

--This is a D Flip-Flop with Asynchronous Clear and Clock Enable(posedge clock).
--Note that the clear input has the highest priority and 
--clock enable having the lowest priority
entity FDCPE1 is
port(Clk :in std_logic;      -- Clock input
    ce :in std_logic;    -- Clock enable input
    clr :in std_logic;  -- Asynchronous clear input
    D :in  std_logic;      -- Data input
    Q : out std_logic      -- Data output
   );
end FDCPE1;

architecture behavioral of FDCPE1 is  --architecture of the circuit.

begin  --"begin" statement for architecture.

process(Clk,clr) --process with sensitivity list.
begin  --"begin" statment for the process.
if(clr = '1') then  --Asynchronous clear input, highest priority
    Q <= '0';
elsif(rising_edge(Clk)) then  
    if(ce = '1') then  --clock enable, lowest priority
        Q <= D;      
    end if;
end if;     
end process;  --end of process statement.

end behavioral;

Testbench Code for the D flipflop:

library ieee;
use ieee.std_logic_1164.all;

--testbench has empty entity
entity tb_FDCPE is
end entity tb_FDCPE;

architecture behavioral of tb_FDCPE is

signal Clk,clr,ce,Q,D : std_logic := '0';
constant Clk_period : time := 10 ns;

begin

--entity instantiation with named association port mapping
FDRSE_uut: entity work.FDCPE1
    port map(Clk => Clk,
        ce => ce,
        clr => clr,
        D => D,
        Q => Q);

--generate clock
Clk_generation: process
begin
    wait for Clk_period/2;
    Clk <= not Clk; --toggle clock when half of clk_period is over
end process;

stimulus: process
begin
    ce <= '1';   D <= '1';  clr <= '0';   
    wait for Clk_period;
    D <= '0';   wait for Clk_period;
    D <= '1';   wait for Clk_period;
    clr <= '1';   wait for Clk_period;
    clr <= '0';   wait for Clk_period;
    ce <= '0';  D <= '1'; wait for Clk_period;  
    D <= '0'; wait for Clk_period;  
    wait;  --testing done. wait endlessly
end process;

end behavioral;

Simulation Waveform from Modelsim:

Schematic from Xilinx Vivado after Synthesis:

Note :- This flipflop entity is named with a "1" at the end because the name "FDCE" stands for a primitive component in Xilinx FPGAs which creates a synthesis error. You can see from the schematic that apart from few input and output buffers, the only flipflop used is called FDCE.

VHDL: Synchronous D Flip-Flop with Testbench

   As per the request from few readers I have decided to post some simple VHDL codes for people who are just starting out with VHDL. This, here is a D Flip-Flop with Synchronous Reset, Set and Clock Enable(posedge clock). The code is well commented I believe, so I wont bore you with more explanations.

Synchronous D flipflop:

--library declaration for the module.
library ieee;
use ieee.std_logic_1164.all;

--This is a D Flip-Flop with Synchronous Reset,Set and Clock Enable(posedge clk).
--Note that the reset input has the highest priority,Set being the next highest
--priority and clock enable having the lowest priority.
entity FDRSE1 is
port(Clk :in std_logic;      -- Clock input
    ce :in std_logic;    -- Clock enable input
    reset :in std_logic;  -- Synchronous reset input
    D :in  std_logic;      -- Data input
    set : in std_logic;   -- Synchronous set input
    Q : out std_logic      -- Data output
   );
end FDRSE1;

architecture behavioral of FDRSE1 is  --architecture of the circuit.

begin  --"begin" statement for architecture.

process(Clk) --process with sensitivity list.
begin  --"begin" statment for the process.
    if(rising_edge(Clk)) then  --This makes the process synchronous(with clock)
        if(reset = '1') then  --synchronous reset, highest priority
            Q <= '0';
        else
            if(set = '1') then  --synchronous set, next priority
                Q <= '1';
            else
                if(ce = '1') then   --clock enable, lowest priority
                    Q <= D;      
                end if;
            end if;
        end if;
    end if;      
end process;  --end of process statement.

end behavioral;

Testbench Code for the D flipflop:

library ieee;
use ieee.std_logic_1164.all;

--testbench has empty entity
entity tb_FDRSE is
end entity tb_FDRSE;

architecture behavioral of tb_FDRSE is

signal Clk,reset,ce,Q,D,set : std_logic := '0';
constant Clk_period : time := 10 ns;

begin

--entity instantiation with named association port mapping
FDRSE_uut: entity work.FDRSE1 
    port map(Clk => Clk,
        ce => ce,
        reset => reset,
        D => D,
        set => set,
        Q => Q);

--generate clock
Clk_generation: process
begin
    wait for Clk_period/2;
    Clk <= not Clk; --toggle clock when half of clk_period is over
end process;

stimulus: process
begin
    ce <= '1';   D <= '1';  
    set <= '0';     reset <= '0';   
    wait for Clk_period;
    D <= '0';   wait for Clk_period;
    D <= '1';   wait for Clk_period;
    reset <= '1';   wait for Clk_period;
    reset <= '0';   wait for Clk_period;
    set <= '1';   wait for Clk_period;
    set <= '0';   D <= '0'; wait for Clk_period;
    ce <= '0';  D <= '1'; wait for Clk_period;  
    wait;  --testing done. wait endlessly
end process;

end behavioral;

Simulation Waveform from Modelsim:

Schematic from Xilinx Vivado after Synthesis:

Note :- This flipflop entity is named with a "1" at the end because the name "FDRSE" stands for a primitive component in Xilinx FPGAs which creates a synthesis error. You can see from the schematic that apart from few logic gates, the only flipflop used is called FDRE.

VHDL: Positive Edge Triggered JK Flip Flop with Testbench

    I want to share the VHDL code for a JK flip flop which is positive edge triggered and has an active high reset input. This flipflop has the following 1 bit inputs: Clock, J, K and reset. The outputs are Q and Qbar. Qbar is always 'not' of Q. 

    The code is written using behavioral modelling. When the reset is low( '0' ) and the value of Clk changes from 0 to 1, we check the value of J and K through if else statements and set the value of Q and Qbar accordingly. 

    The reset input in this JK flipflop is said to be asynchronous because its value is checked independent of the state of the clock signal.

VHDL Code for JK Flipflop:

--libraries to be used are specified here
library ieee;
use ieee.std_logic_1164.all;

--entity declaration with port definitions
entity JK_flipflop is
port(Clk : in std_logic;  --positive edge triggered
    J, K: in std_logic;
    reset: in std_logic;  --active high reset
    Q, Qbar: out std_logic
    );
end JK_flipflop;

--architecture of entity
architecture Behavioral of JK_flipflop is

--temporary signals.
--they are used because, output ports cannot be read in the VHDL versions prior to 2008.
signal qtemp, qbartemp : std_logic := '0';

begin

--assign the temporary signals to corresponding output ports.
--'Qbar' is always 'not' of 'Q'.
Q <= qtemp;
Qbar <= qbartemp;

--process for JK flip flop
process(Clk,reset)
begin
if(reset = '1') then           --Reset the output when reset is high
    qtemp <= '0';
    qbartemp <= '1';
elsif(rising_edge(clk)) then
    if(J='0' and K='0') then       --No change in the output
        NULL;
    elsif(J='0' and K='1') then    --Set the output Q.
        qtemp <= '0';
        qbartemp <= '1';
    elsif(J='1' and K='0') then    --Reset the output Q.
        qtemp <= '1';
        qbartemp <= '0';
    else                           --Toggle the output Q.
        qtemp <= not qtemp;
        qbartemp <= not qbartemp;
    end if;
end if;
end process;

end Behavioral;

Testbench code for JK Flipflop:

--library declarations
library ieee;
use ieee.std_logic_1164.all;

--this is how entity for your test bench code has to be declared.
entity testbench is
end testbench;

architecture behavior of testbench is

--Signal declarations
signal Clk,J,K,reset,Q,Qbar : std_logic := '0';
-- Clock period definitions
constant Clk_period : time := 10 ns;

begin

-- Instantiate the Unit Under Test (UUT). 
--This style is known as entity instantiation with named association
UUT : entity work.JK_flipflop 
    port map(Clk => Clk,
        J => J,
        K => K,
        reset => reset,
        Q => Q,
        Qbar => Qbar);

--Generate Clk with a period of 'Clk_period'
Clk_generation: process
begin
    Clk <= not Clk;  --toggle 'Clk' when half 'Clk_period' is over.
    wait for Clk_period/2;
end process;

-- Stimulus process
stimulus: process
begin        
    --change J and K and wait for a Clock period to see the changes
    J<='1'; K<='0'; wait for Clk_period;
    J<='1'; K<='1'; wait for Clk_period;
    J<='0'; K<='1'; wait for Clk_period;
    J<='0'; K<='0'; wait for Clk_period;
    J<='1'; K<='0'; wait for Clk_period;
    --apply reset input and change J and K.
    reset <='1';
    J<='1'; K<='1'; wait for Clk_period;
    J<='0'; K<='1'; wait for Clk_period;
    --reset is made 'low' again.
    reset <='0';
    --now onwards, Q will keep toggling between 1 and 0.
    J<='1'; K<='1'; wait for Clk_period;
    wait;
end process;

end;

Simulation Waveform:

The codes were simulated in Modelsim. This is a screenshot of the waveform.

    The code was synthesized using Xilinx ISE. The RTL schematic of the design is shown below:

    In the schematic FDPE represents a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). Similarly FDCE represents a single D-type flip-flop with data (D), clock enable (CE), and asynchronous clear (CLR) inputs and data output (Q). 

Note :- Use RTL Viewer to get a closer look on how your design is actually implemented in hardware.