Concatenation Operator in VHDL

     Many VHDL programmers doesnt know that there is a operator available in VHDL for doing concatenation.But there is one. It is written as '&'.
Let us see some usages of this operator.

signal w, x, y, z :std_logic:='0';
signal t : std_logic_vectoR(1 downto 0);
t<= (w and x) & (y and z);

--this is same as
t(1) <= w and x;
t(0) <= y and z;

Remember that the left hand side variables on the RHS belong to the MSB of the left hand side operand.

     Integers cannot be concatenated directly,but they can be in the following way.Here is an example to show how you will concatenate two integers to form and std_logic_vector.

signal t : std_logic_vector(31 downto 0);
constant a: integer := 23;
constant b: integer := 456;
-- conv_std_logic_vector(signal_name, number_of_bits)
t <= conv_std_logic_vector(a, 16) & conv_std_logic_vector(b, 16);

Another example:

signal a: std_logic_vector(0 to 3):="1111";
signal b: std_logic_vector (0 to 7):= (others => '0');
--this statement will make the MSB 4 bits to zero and LSB 4 bits to one.
b<="0000" & a;

The operator is very useful when comes to checking a group of bits inside a case statement.The following example illustrates the concept:

process(bit0,bit1,bit2,bit3)
   variable bitcat : std_logic_vector(3 downto 0);
begin
   bitcat := bit0 & bit1 & bit2 & bit3; --concatenation
   case bitcat is
      when "0001" => xxx <= 1;
      when "0010" => xxx <= 3;
      when others => xxx <= 4;
   end case;
end process;

These are some of the few  situations where '&' operator can be used efficiently.If you know some more free to post them in the comment section.