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Friday, March 26, 2010

Concatenation Operator in VHDL

     Many VHDL programmers doesnt know that there is a operator available in VHDL for doing concatenation.But there is one. It is written as '&'.
Let us see some usages of this operator.

signal w, x, y, z :std_logic:='0';
signal t : std_logic_vectoR(1 downto 0);
t<= (w and x) & (y and z);

--this is same as
t(1) <= w and x;
t(0) <= y and z;

Remember that the left hand side variables on the RHS belong to the MSB of the left hand side operand.

     Integers cannot be concatenated directly,but they can be in the following way.Here is an example to show how you will concatenate two integers to form and std_logic_vector.

signal t : std_logic_vector(31 downto 0);
constant a: integer := 23;
constant b: integer := 456;
-- conv_std_logic_vector(signal_name, number_of_bits)
t <= conv_std_logic_vector(a, 16) & conv_std_logic_vector(b, 16);

Another example:

signal a: std_logic_vector(0 to 3):="1111";
signal b: std_logic_vector (0 to 7):= (others => '0');
--this statement will make the MSB 4 bits to zero and LSB 4 bits to one.
b<="0000" & a;

The operator is very useful when comes to checking a group of bits inside a case statement.The following example illustrates the concept:

   variable bitcat : std_logic_vector(3 downto 0);
   bitcat := bit0 & bit1 & bit2 & bit3; --concatenation
   case bitcat is
      when "0001" => xxx <= 1;
      when "0010" => xxx <= 3;
      when others => xxx <= 4;
   end case;
end process;

These are some of the few  situations where '&' operator can be used efficiently.If you know some more free to post them in the comment section.


  1. I think in cancatation t<= (x and w) & (y and z). result of y and z is assigned to LSB of t and result of x and w is assigned to MSM i.e.t(1)

  2. @Ravindar : yeah.. you are right.Sorry for the typing mistake.I have corrected it.Some more examples are here...

    signal a : unsigned(1 downto 0);
    signal b : unsigned(0 to 1);
    a <= '1' & '0';
    b <= '1' & '0';
    --this is same as:
    a(1) <= '1';
    a(0) <= '0';
    b(1) <= '0';
    b(0) <= '1';

    thanks for the comment.

  3. A useful tip -- watch out for operator order. eg "x & y and z & w" is the same as (x&y) and (z&w). Its easy to accidently read it as x & (y and z) & w. This usually results in a synthesis error, as its unlikely the dimensions will match.

  4. Hi I have a problem abd I am not sure what is wrong.

    entity LOOP is
    Port ( S1 : in STD_LOGIC;
    S2 : in STD_LOGIC;
    S3 : in STD_LOGIC;
    S4 : in STD_LOGIC;
    OUT1 : out STD_LOGIC;
    OUT2 : out STD_LOGIC;
    OUT3 : out STD_LOGIC);
    end LOOP;

    architecture Behavioral of LOOP is

    Signal input: std_logic_vector (1downto 0);


    input <= S1 & S2;


    if (input= '00') then

    elsif (input = '01') then
    elsif (input = '10') then



    end if;

    OUT3= S3 AND S4;

    Please help!

    end Behavioral;

    1. you cant use reserved word as a entity name..(loop).
      you must use process declaration part in between two begin comments.
      And another fault is "".if the binary elements are in array, you must declare double quotations like input = "01".
      And finally declare end process statement before on end behavioral..

  5. Please tellme some one?
    when the combine two VHDL Together, what is the name of that?


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