VHDL: 4 bit Comparator Using Behavioral Level Modelling with Testbench

    I want to share the VHDL code for a 4 bit comparator implemented using if.. else.. statements. The entity port has two 4-bit inputs and three 1-bit wires.

    The three outputs are less, equal, greater. The second number is compared with the first number and one and ONLY ONE of these output signal is set high.

VHDL Code for a 4 bit Comparator:

--libraries to be used are specified here
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--entity declaration with port definitions
entity compare is
port(num1 : in unsigned(3 downto 0);  --1st number
    num2 : in unsigned(3 downto 0);  --2nd number
    less : out std_logic;   -- indicates first number is smaller
    equal : out std_logic;   -- both are equal
    greater : out std_logic    -- indicates first number is bigger
);
end compare;

--architecture of entity
architecture Behavioral of compare is

begin

--Behavioral modelling to compare two 4 bit numbers.
process(num1,num2)
begin    -- process starts with a 'begin' statement
    if (num1 > num2 ) then  --checking whether num1 is greater than num2
        less <= '0';
        equal <= '0';
        greater <= '1';
    elsif (num1 < num2) then    --checking whether num1 is less than num2
        less <= '1';
        equal <= '0';
        greater <= '0';
    else     --checking whether num1 is equal to num2
        less <= '0';
        equal <= '1';
        greater <= '0';
    end if;
end process;   -- process ends with an 'end process' statement

end Behavioral;

The process above is a combinatorial process. Every time any of the signals in the process sensitivity list is changed, the process is 'invoked' and the logic inside is as if 'executed'. This explanation is just for beginners to get an inkling on what is going on. But don't take it too seriously, as you will need to refine this understanding as you get to know more of how VHDL works.

Testbench code for 4 bit Comparator:

--library declarations
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--testbench entity is always empty. no ports to be declared here.
entity testbench is
end testbench;

architecture behavior of testbench is

--internal signals
signal num1,num2 : unsigned(3 downto 0) := (others => '0');
signal less,equal,greater :  std_logic:='0';

begin

--entity instantiation with named association style
uut : entity work.compare 
    port map(num1 => num1,
        num2 => num2,
        less => less,
        equal => equal,
        greater => greater);

stimulus : process
begin
    --'to_unsigned' converts the integer into unsigned type
    num1 <= to_unsigned(2,4);  
    num2 <= to_unsigned(9,4);  
    wait for 2 ns;

    num1 <= to_unsigned(9,4);  
    num2 <= to_unsigned(2,4);  
    wait for 2 ns;

    num1 <= to_unsigned(10,4);  
    num2 <= to_unsigned(10,4);  
    --more input combinations can be given here.
    wait;
end process stimulus;

end;

Simulation Waveform:

The codes were simulated in Modelsim. This is a screenshot of the waveform.

RTL Schematic:

The code was synthesized using XILINX ISE XST . The RTL schematic of the design is shown below:

Note :- Use RTL Viewer to get a closer look on how your design is actually implemented in hardware.