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Sunday, March 28, 2010

Fixed Point Operations in VHDL : Tutorial Series Part 1

     You must have heard about library named fixed_pkg.In terms of complexity this library can be placed some where between integer math and floating point maths.I have decided to write a series of tutorials about the usage of fixed_pkg library.The library helps to handle fractional numbers with ease.
The library can be downloaded from here.

In the first part of this tutorial, I will give an introduction about the library and the new data types available for use.

How to use this library in your module?
Add the following two lines to your code(the place where you usually add the libraries):

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

What are the new data types available in the package?
     FIXED_PKG defines two new data types.They are UFIXED ( for unsigned fixed point) and SFIXED (for signed fixed point).

How to declare signals?
Say you want a fixed point unsigned signal with 'a' bits for decimal part and 'b' bits for fractional part,then you can declare them as follows:

signal example : ufixed( a-1 downto -b);
--an example
signal example : ufixed (3 downto -4);

Here the signal 'example' has 4 bits for decimal part and 4 bits for fractional part.
example = 9.75 = "1001.1100" or simply example ="10011100".

For signed numbers we use "sfixed" while declaring the signals.Signed numbers are stored as 2's complement format.

--an example for signed fixed point type.
signal example : sfixed(4 downto -4);

     Here the signal 'example' has 5 bits of decimal part and 4 bits for fractional part.
example = -9.75 = "101100100".This is got by taking 2's complement of binary value of 9.75.The MSB bit '1' indicates the number as negative.

If you declare the signal as sfixed and still store a positive value(say 9.75) then it has the same kind of storage format as ufixed.

--an example
signal example : sfixed(4 downto -4);
--If 'example' contains 9.75 then it is storage as "01001.1100".

     Remember that you declare the signals with sufficient width so that values are get stored correctly.If the width is not enough then the signal may get rounded off.


  1. hi, i tried using the library you have given above but i get the following error in quartus:

    Error (10481): VHDL Use Clause error at TEMP_READER.vhd(9): design library "ieee_proposed" does not contain primary unit "fixed_pkg"

    why? i copied the vhdl file to the library folders

  2. @Thabang : see this link for the error you have got:
    Mostly this will be a problem with Quartus.They may not have updated their software for this relatively new library.
    For me it worked fine in Xilinx, but gave some problems during synthesis.

  3. This tutorial was inspired from fixed_pkg" documentation by David Bishop.The original document can be downloaded from

  4. Hi, I'm trying to simulate a multiplication of fixed-point numbers in ISIM Xilinx ISE 12.3 and is giving me the following error:

    HDLCompiler:0 - "Unknown" Line 0: cannot open file "/opt/Xilinx/12.3/ISE_DS/ISE/vhdl/hdp/lin64/ieee_proposed/fixed_float_types.vdb" for writing

    this file does not exist in that folder, How I can do to fix it?.

    Another question is how I can use the multiplier of core generator with fixed-point numbers? I'm trying to convert a std_logic_vector, but don't know if i can do that (so I need to do the simulation).

  5. @Juan : Try this,
    1)Download this file and store it in the project directory.

    2)Now replace the following lines :
    library ieee_proposed;
    use ieee_proposed.fixed_pkg.all

    with thesee:
    library work;
    use work.fixed_pkg.all

    Core generator component can be instantiated in your design.

  6. I am trying to multtiply two real number by using this library simulation is giving perfectio result... but it gives error during synthesis. like....((constant fixedsynth_or_real : BOOLEAN; -- differed constant)) has noo value.. what shud i do to make it synthesis able

  7. Please, how to use this package in modelsim (student edition) and in Xlinix ISE 10.1
    I mean how to add and compile them as mentioned above in the library named ieee_proposed?

  8. i am using fixed point multiplication i am gettig error can i use this can i add it to my project...please help me...

  9. hi I have a problem on adding a libraries
    Line 7. Library ieee_proposed cannot be found.
    Line 8. Library ieee_proposed is not declared.

    what should I do?

  10. hiii...i hav getting following errors during fixed point operation ..i am working on fast fourier transform architecture..
    Line 7. Library ieee_proposed cannot be found.
    Line 8. Library ieee_proposed is not declared.
    above errors obtained when when device not selected spartan 6
    following errors are occur after test bench creation..
    Attribute instance_name cannot be used here.
    Wrong index type for to_stdlogicvector...
    i have seen solution on xilinx website bt i hav not get it proprly..the soln given them is as follow..
    """I have got the answare. Using the Xilinx (ISE 11.1) version of the fixed_pkg from David Bishop with -use_new_parser yes otpion in XST, will just gave 3 warnings, allowing the synthesis to be done..."""" i hav not got what they mean...plz help me...

  11. can some one help me with the vhdl coding for fixed point algorithm...

  12. I am using Xilinx ISe 14.5
    How to add the library to my project. I added source file but i get the following error when synthesizing:
    library ieee_proposed cannot be found and library ieee_proposed is not declared

  13. i added the following to my project after adding the two packages files (fixed_pkg, fixed_float_types, float_pkg) to the project folder and i got 131 error in (fixed_pkg) file !!!!

    what is the solution for this?

  14. i use xilinx 14.2....... i get error message saying .... library ieee_proposed cannot be found and library ieee_proposed is not declared

  15. I too have the same errors unable to find the library.Please kindly post a video of adding the library to the project directory with the required steps.Thank you for your kind cooperation @vipin


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