VHDL coding tips and tricks: Reading and Writing files in VHDL - An easy way of testing design

Wednesday, March 31, 2010

Reading and Writing files in VHDL - An easy way of testing design

      If your design has a large array of inputs then you cannot put them in the testbench program.It will make the testbench code very difficult to read.In such cases it is advisable to store the inputs in a text file and read it from that file.Even you can have an output file,where you can store your output values.

     In the example I have shown,I have two files.First one is named as "1.txt" and is my input file.The values will be read from this file and simply copied to the second file named "2.txt". The example is meant for just a basic introduction for file handling in VHDL.There are pretty large number of options when it comes to file handling,but I will post them in future.

--include this library for file handling in VHDL.
library std;
use std.textio.all;  --include package textio.vhd

--entity declaration
entity filehandle is
end filehandle;

--architecture definition
architecture Behavioral of filehandle is
--period of clock,bit for indicating end of file.
signal clock,endoffile : bit := '0';
--data read from the file.
signal    dataread : real;
--data to be saved into the output file.
signal    datatosave : real;
--line number of the file read or written.
signal    linenumber : integer:=1;


clock <= not (clock) after 1 ns;    --clock with time period 2 ns

--read process
reading :
    file   infile    : text is in  "1.txt";   --declare input file
    variable  inline    : line; --line number declaration
    variable  dataread1    : real;
wait until clock = '1' and clock'event;
if (not endfile(infile)) then   --checking the "END OF FILE" is not reached.
readline(infile, inline);       --reading a line from the file.
  --reading the data from the line and putting it in a real type variable.
read(inline, dataread1);
dataread <=dataread1;   --put the value available in variable in a signal.
endoffile <='1';         --set signal to tell end of file read file is reached.
end if;

end process reading;

--write process
writing :
    file      outfile  : text is out "2.txt";  --declare output file
    variable  outline  : line;   --line number declaration  
wait until clock = '0' and clock'event;
if(endoffile='0') then   --if the file end is not reached.
--write(linenumber,value(real type),justified(side),field(width),digits(natural));
write(outline, dataread, right, 16, 12);
-- write line to external file.
writeline(outfile, outline);
linenumber <= linenumber + 1;
end if;

end process writing;

end Behavioral;

The contents of files 1.txt and 2.txt are shown below:

Now let us discuss about the textio.vhd package and its general features.

It offers the following new data types:

type LINE is access STRING;  -- A LINE is a pointer to a STRING value
type TEXT is file of STRING; -- A file of variable-length ASCII records.
type SIDE is (RIGHT, LEFT);   -- For justifying output data within fields.
subtype WIDTH is NATURAL;     -- For specifying widths of  output fields.

It offers a large number of functions to read and write to a file.You can see the list of all functions and the arguments used here.

In the example program given above I have two different processes,one for reading from the file and another for writing into the file.
endfile() is a function which is used to check whether the end of the file is reached.It returns a '1' when end of file is reached.
The data cannot be read directly into a signal.That is why I have first read it into a variable and then assigned it into a signal.
Every time you write something into the file or read something from the file,the line number is internally incremented.

Note :- One advantage of file handling in VHDL is that,you can test a large number of input combinations for checking the integrity of your design.Sometimes the automatically generated test cases(with the help of a program) can be easily used without much changes in the testbench code.


  1. hi,
    I tried same approach to read and write file..
    my compiler setting is for vhdl93
    error msg was smthing like : this is for vhdl87

    wat i came to know is that in vhdl93 the way to read and write file is different(ref: appendix of Parry),,
    can u plz tell us that hw to do it for vhdl93 as part of my design can only be compiled using vhdl93 only,,
    thanks for writing great posts

  2. @hank : check this link now,for the file reading and writing codes.I will update my blog with a relevant post later on the same topic.

  3. hi,,
    thanks for the nice link.
    I have one more doubt..
    watever literature i saw on this topic..most of them have one thing common: a part of code is with the rising edge and another part is with the falling edge..like in ur above example u r doing writitng on falling edge..
    why is it happening dis way??plz explain..
    I was planning something in which i can read a file and apply those i/p directly on one of my ports ..the whole thing on rising edge only..
    suggest smthing..

  4. Dont worry about the rising and falling edge thing. Its just that I am waiting for some time for updating the signals. Read -> wait for some time -> the write.

    check the code in the new link. It doesnt require any thing like that. Only thing you have to make sure is that, value written to the file is proper.You can do it in whichever way you want.I introduced here a half clock cycle delay.If you want you can use one whole clock cycle delay.

  5. very nice blog..
    how to make the comparison. Read -> Process -> Write. For example: if the files 1.txt contains:
    with the formula if the input >= 3 then the output = 5 else the output = 0
    i want to make the output file 2.txt be :

    I always fail when modifying the above program, whether it's because if statemens I still do not know.
    thankyou if you want to help..

  6. hii.. this is very helpful link, thanx for your information. I've tried several ways to get results like I want. for example, by using the following code:
    signal X : integer :=3;
    if (endoffile = '0') then
    dataread =0 when dataread <=X else dataread =5;
    write(outline, dataread, right, 3, 1);
    linenumber <= linenumber + 1;
    end if;

    what's wrong with my structure code. command error on modelsim -> near "=": expecting <= or :=

  7. @rino : You can simply modify the above program to get what you want(comparison). Read an element.And inside a if condition write whatever value you want to write to the other file.
    If you need help with your projects contact me.

  8. OK..
    i'm finished my project with comparison. the problem for how to make the comparison just if condition. same with you said. thanx for guide. i like this blog

  9. Hello, I'm Korean Student studying VHDL.
    Sorry for my english....

    I'm making Drum loop machine for my term project.
    It loads wav files as drum beat from sd card then play it.

    so I want to use SD Card
    But I can't find any appropriate example or solutions....

    May I borrow your hand???

    1. Hi,

      Thanks for this interesting and practical VHDL example. I spend a lot of my time at work writing VHDL components and I'm always looking for better ways of testing them. I have previously discounted text file driven testing because of the complexities of handling strings and files in the language, however your example makes it look quite simple!

      I look forward to reading more posts in the future

      Chris, www.beesnotincluded.com

  10. hi
    how we can simulate this program..
    can you tell me procedure what i have to write in signal and wave form window...

    1. you dont need to create a waveform.. simply click on "simulate".

    2. Hi vipin,

      I click the simulate but the output file is empty although i did set the input file just follow the code..

  11. hi....wher to store input and output file prior to simulating??????

    1. store it in text files. the name of the file names are given in the code.

  12. Where on my computer do I save the text file? Because whenever i try to simulate the code I get the following error:

    ** Error: (vsim-7) Failed to open VHDL file "1.txt" in rb mode.
    # No such file or directory. (errno = ENOENT)
    # Time: 0 ns Iteration: 0 Instance: /read_file

    Please what do I do to solve this problem?

  13. hii i want to read 65536 pixel values how to read it? this wil read?? for abve tsst bench?

    type ram2 is array (1 to 65536) of integer;
    signal pixel:ram2;


    if (rst='1') then
    if (clk'event and clk='1') then
    for i in 1 to 65535 loop
    pixel(i) <= conv_integer(datain);

    end loop;
    end if;
    end if;

    end process;

  14. I want know how to write VHDL code for ASCII to Binary and vice-versa code. help me....

  15. Hi,

    Thanks for the post. I want to write to a text file which isn't empty in my VHDL testbench without losing that data. every time that I do that it will start writing from the first line and clear the whole previous data. Could you please tell me if its possible?


  16. In which directory should the .txt files be stored?

  17. Hi, I tried to compile this VHDL program, but I have an error in this line :
    signal dataread : real;

    The error message is :
    Error (10414): VHDL Unsupported Feature error at filehandle.vhd(14): cannot synthesize non-constant real objects or values

    How can we fix this error please?

  18. This comment has been removed by the author.

  19. Hey guys, I am trying to include these functions in my test bench but I am getting the following error regarding both file infile : text is in ""; and file outfile : text is out "";
    -------> expecting an expression or operand

    Does anybody have an idea where this could come from?

  20. This comment has been removed by the author.

  21. Thank you so much. This code helped me a lot. How to do the same thing for a 2D array ? Please reply soon.

  22. is this code works for reading hexadecimal values..??

  23. I have data I want to read into a fifo from a text file. My prof says the text file has to be simulated as a testbench, but that still leaves me with the fifo implementation file and fifo simulation file. How do I run the two testbenches that require communication with the same fifo module? In other words, is there a way to identify the simulation running the text read as a "component" testbench?.. similar to how one would run a component module in a testbench? Any help is appreciated. Thx.