A synthesizable delay generator instead of 'wait for' statement

There are many situations in which you may need to activate a process after a certain delay or at fixed time intervals.If you want to do simulation alone for your design then you can simply use "wait for" statement to call a delay routine.But this keyword is not synthesizable.So what will you do in such situations?
A simple delay routine,which is synthesizable, can be designed using the properties of a "MOD-n counter".A MOD-n counter can be used to generate a frequency of (f / n) using a frequency 'f'. The code for generating such a delay is given below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
  port (clk : in std_logic;
--delay to be generated.
        a : in std_logic_vector(31 downto 0);  
--this is a pulse to notify that time interval equal to delay is over.
        flag : out std_logic
    );
end test;

architecture Behavioral of test is
signal count :integer:=0;
begin
process(clk)
begin
if(clk'event and clk='1') then
count <= count +1;   --increment counter.
end if;
--see whether counter value is reached,if yes set the flag.
if(count = conv_integer(a)) then
count <= 0;
flag <='1';
else
flag <='0';
end if;
end process;

end Behavioral;

The module has 2 inputs0- clock and a vector which determines the amount of delay to be generated.
Say you want a 100 ns delay.Now say your clk frequency is 1 GHz,that is your clock period is 1 ns.So the value of 'a' should be equal to (100 / 1) = 100.When the counter counts till 100, it sends a pulse to notify.Below is an example of how to do it :

---- a program which uses a delay routine of 100 ns.
architecture Behavioral of your_module is
signal flag : std_logic :='0';
signal delay_needed : std_logic_vector(31 downto 0);
delay_needed <= "00000000000000000000000001100100";  --100 in binary.
inst_delay : test port map(clk,delay_needed,flag);
begin

process(flag)
begin
if(flag'event and flag='1') then
output <= calculated;  -- this line is executed only once in 100 ns.
end if;
end process;

end Behavioral;

This small code can be used under many situations,like :
    1) To run some parts of your design at a lesser clock frequency than your system clock.
    2) To create a delay between some of the processes.

The range of delay values can be increased by increasing the size of 'a'.Also the maximum error in the delay produced is equal to time period of input clock.