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Friday, March 12, 2010

Xilinx ISE Help : Using RTL and Technology Schematics

     This tutorial deals with the Xilinx ISE-synthesis tool.I have assumed that you know, how to start a project in Xilinx ISE and run a simulation etc...  
     Once you have completed simulation for your design successfully you want to test it in hardware.The first step to this is synthesizing your code.The synthesis of your VHDL code is done by XST(Xilinx Synthesis Technology) tool,which is included in Xilinx ISE software.XST creates Xilinx-specific net-list files called NGC files.Remember that NGC files are not always same,even for the same VHDL code.Depending upon the family and device you have chosen you will get different NGC files.Each NGC file has two parts : logical design data and constraints.

     Let us learn how to synthesis a code and infer the reports generated by the software.Copy the 'counter' program from here.This is a 4 bit counter with reset input.Add this code to your Xilinx ISE project and click on "Synthesis-XST".This will start the Synthesis process.Once the synthesis is done without any errors, you can get a lot of details from the files generated by synthesis process.

1) To get an overall synthesis report,click on "View Synthesis Report".This will open a file in a new tab,with extension .syr.From this file you can get the following information:
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) Timing Summary

      Also the synthesis results can be seen by viewing two type of schematics:
2)Click on "View RTL schematic" and you will see the RTL net-list generated by XST. A file will be opened with the extension .ngr.This file is meant for viewing only.So you can't edit it.This file shows a schematic representation of the pre-optimized design in terms of generic symbols that are independent of the targeted Xilinx device, for example, in terms of adders, multipliers, counters, AND gates, and OR gates etc.The .ngr schematic in this case will look like this:


     You can see that there are no hardware elements present in the schematic.For knowing what hardware elements have been used follow step 3.
3) Click on "View Technology Schematic".You can see the following image opened in a new tab,with an extension .ngc.This file contains the detailed information of the exact elements used in FPGA chip.See the figure below:


     From the above diagram you can infer that,your design has used one 4 input LUT(Lockup Table),one 3 input LUT,one 2 input LUT and 4 FDC(a D flip-flop with asynchronous clear input).Some other elements used are input buffer,output buffer,inverters etc.
   Now double click on any one of the LUT's(say on LUT2).A new window will open as shown below.This window provides the following information.
1)The schematic of the gate elements used inside that particular LUT.
2)The Truth Table of the function implemented by that particular LUT.
3)The Karnaugh map of the truth table.



     Sometimes these schematics can be used to find out how exactly your code is mapped into hardware.For students in VLSI or people with an interest in FPGA designs ,this tool is a boon.I was very much excited when I first saw these schematics.

Note :- In the RTL schematic if you don't see some of the component names then visit this link for more information.

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