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Wednesday, March 10, 2010

Basic model of FIFO Queue in VHDL

   Here is a basic model of FIFO(first in first out) queue. I have made some assumptions about the operation of this FIFO.I have assumed that my writing speed is faster than my reading speed of the queue.The comments are provided where ever needed.The size of the FIFO is 256 * 8 bit.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fifo is
port (  clk : in std_logic;
          enr : in std_logic;   --enable read,should be '0' when not in use.
          enw : in std_logic;    --enable write,should be '0' when not in use.
          dataout : out std_logic_vector(7 downto 0);    --output data
          datain : in std_logic_vector (7 downto 0);     --input data
          empty : out std_logic;     --set as '1' when the queue is empty
          full : out std_logic     --set as '1' when the queue is full
         );
end fifo;

architecture Behavioral of fifo is
type memory_type is array (0 to 255) of std_logic_vector(7 downto 0);
signal memory : memory_type :=(others => (others => '0'));   --memory for queue.
signal readptr,writeptr : std_logic_vector(7 downto 0) :="00000000";  --read and write pointers.
begin
process(clk)
begin
if(clk'event and clk='1' and enr ='1') then
dataout <= memory(conv_integer(readptr));
error <= '0';
readptr <= readptr + '1';      --points to next address.
end if;
if(clk'event and clk='1' and enw ='1') then
memory(conv_integer(writeptr)) <= datain;
writeptr <= writeptr + '1';  --points to next address.
end if;
if(readptr = "11111111") then      --resetting read pointer.
readptr <= "00000000";
end if;
if(writeptr = "11111111") then        --checking whether queue is full or not
full <='1';
writeptr <= "00000000";
else
full <='0';
end if;
if(writeptr = "00000000") then   --checking whether queue is empty or not
empty <='1';
else
empty <='0';
end if;
end process;

end Behavioral;

     The above program shows an approach towards modeling a FIFO.The actual FIFO used in communication protocols etc is more complex than the one given here.I recommend you to use CoreGen software from Xilinx for,generating code for complex FIFO's.

11 comments:

  1. --these are evil:
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    --use this instead:
    use ieee.numeric_std.all;

    ReplyDelete
  2. @anonymous : please see this post,
    http://vhdlguru.blogspot.com/2010/03/why-library-numericstd-is-preferred.html

    ReplyDelete
  3. library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity fifo is
    GENERIC
    (
    ADDRESS_WIDTH : integer:=8;---8 bit
    DATA_WIDTH : integer:=32 ---32 bit
    );

    port ( clk : in std_logic;
    reset : in std_logic;
    enr : in std_logic; --enable read,should be '0' when not in use.
    enw : in std_logic; --enable write,should be '0' when not in use.
    dataout : out std_logic_vector(DATA_WIDTH-1 downto 0); --output data
    datain : in std_logic_vector (DATA_WIDTH-1 downto 0); --input data
    empty : out std_logic; --set as '1' when the queue is empty
    err : out std_logic;
    full : out std_logic --set as '1' when the queue is full
    );
    end fifo;

    architecture Behavioral of fifo is

    type memory_type is array (0 to ((2**ADDRESS_WIDTH)-1)) of std_logic_vector(DATA_WIDTH-1 downto 0);


    -----distributed-------
    signal memory : memory_type ;-- :=(others => (others => '0')); --memory for queue.-----
    signal readptr,writeptr : std_logic_vector(ADDRESS_WIDTH-1 downto 0); --read and write pointers.
    signal full0 : std_logic;
    signal empty0 : std_logic;

    begin
    full <= full0;
    empty <= empty0;

    fifo0: process(clk,reset)
    begin
    if reset='1' then

    readptr <= (others => '0');
    writeptr <= (others => '0');
    empty0 <='1';
    full0<='0';
    err<='0';


    elsif rising_edge(clk) then

    if (writeptr + '1' = readptr) then
    full0<='1';
    else
    full0<='0';
    end if ;

    if (readptr = writeptr ) then
    empty0<='1';
    else
    empty0<='0';
    end if ;

    if (empty0='0' and enr='1') or (full0='0' and enw='1') then
    err<='1';
    end if ;

    if enw='1' and full0='0' then
    memory (conv_integer(writeptr)) <= datain ;
    writeptr <= writeptr + '1' ;
    end if ;

    if enr='1' and empty0='0' then
    dataout <= memory (conv_integer(readptr));
    readptr <= readptr + '1' ;
    end if ;

    end if;

    end process;
    end Behavioral;




    fix fifo doal port ram

    ReplyDelete
  4. it is ram block and not distributed in my comment

    ReplyDelete
  5. This example is wrong, please correct or remove it; many people have copied it from your website and are wasting a lot of time wondering why it does not work.

    One of the reasons why it is wrong: to generate the "empty" and "full" flags, signals "readptr" and "writeptr" should be compared with one another, and NOT with absolute values. Cohen's example above is on the right direction.

    To be fair, the presented code is a FIFO in the sense that the first value in is the first value out, but it requires a reset every 256 elements. This is *not* what people want, in 99.99% of the cases.

    ReplyDelete
  6. Agree with Jasinski. The FIFO full/empty conditions should be more like the following: (note that in this example, the pointers are definted as integers by the ieee.numeric.std)

    if(writeptr = readptr) then
    FIFO_EMPTY <='1';
    else
    FIFO_EMPTY <='0';
    end if;

    if(writeptr = (readptr - 1)) then
    FIFO_FULL <='1';
    else
    FIFO_FULL <='0';
    end if;

    The empty condition occurs when you read the last value written, hence comparing them to each other. Full occurs when you write so many values that you fill up to one less than the last value read.

    ReplyDelete
  7. roei cohen variant is mostly correct except one thing: active "full" value will be sensed by wrighting block on 1 clk later, so it will try to write data to FIFO when it's already restricted.

    ReplyDelete
  8. I think in stead of error <=0; ,enr<=0; will be there;

    ReplyDelete
  9. hi I need a READY QUEUE with priority any help?????????

    ReplyDelete

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